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3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc - 1 - features ? works with 1.25v ~ 5.5v v in ? ultra low dropout voltage ? low quiescent current ? excellent line and load regulation ? guaranteed output current of 3.0a ? adjustable output voltage down to 0.8v ? v out power ok signal ? logic controlled shutdown option ? over-temperature/over-current protection ? -40 to 125 junction temperature range application ? motherboards and graphic cards ? microprocessor and chipset power supplies ? peripheral cards ? low voltage digital ics ? high efficiency linear regulators descripsion the tj47300 is a 3.0a high performance ultra low- dropout linear regulator ideal for powering core voltages of low-power microprocessors. the tj47300 implements a dual supply configuration allowing for very low output impedance. the tj47300 requires a bias input supply and a main input supply, allowing for ultra-low input voltages on the main supply rail. the input supply operates from 1.25v to 5.5v and the bias supply requires between 3v and 5.5v for proper operation. the tj47300 delivers high current and ultra-low-dropout output voltage as low as 0.8v for applications where v out is very close to v in . the tj47300 is developed on a cmos technology which allows low quiescent current operation independent of output current. this technology also allows the tj47300 to operate under extremely low dropout conditions. sop \ 8 \ pp ? ? ? ordering information device package TJ47300GDP sop8-pp absolute maximum ratings characteristic symbol min. max. unit input supply voltage (survival) v in -0.3 6 v enable input voltage (survival) v en -0.3 6 v bias supply voltage (survival) v bias -0.3 6 v output voltage (survival) v out -0.3 v in +0.3 v lead temperature (soldering, 5 sec) t sol 260 storage temperature range t stg -65 150 operating junction temperature range t jopr -40 125 package thermal resistance * ja-sop8-pp 68 oc/w * calculated from package in still air, mounted to 2.6mm x 3.5 mm(minimum foot print) 2 layer pcb without thermal vias per jesd5 1 standards.
3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc 2 ordering information package order no. description package marking compliance supplied as sop8-pp TJ47300GDP 3.0a, enable, adjustable, power ok tj47300g rohs, halogen free reel ordering information (continued)
3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc 3 pin configuration sop8-pp pin description pin no. pin name pin function 1 pok power ok indication. this pin is an open -drain output and is set high impedance once v out reaches 92% of its rating voltage. 2 en enable input. pulling this pin be low 0.4v turns the regulator off. do not float 3 in power input. this pin is the drain input to the power device that supply current to output pin. 4 bias supply input for internal circuit. input bi as voltage for powering all circuitry on the regulator except the output power tr. 5 nc no connection. 6 out power output. this pin is power output of the device. 7 fb feedback voltage. a resistor divider from the output to gnd is used to set the regulation voltage as v out = 0.8v x (1+r2/r1) 8 gnd ground - thermal exposed pad connect to ground.
3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc 4 block diagram typical application
3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc 5 electrical characteristics unless otherwise specified: v bias = 5v, v in = v o(nom) + 1v, v en =v bias , i l = 10 ma, t a =25 . parameter symbol test condition min. typ. max. unit power input voltage v in v out =v ref 1.25 - 5.5 v bias input voltage v bias v out =v ref 3.0 - 5.5 v reference voltage v ref v bias =v in =v en =5.0v, i out =10ma, v out =v ref 0.784 0.8 0.816 v v in line regulation (note 1) v line(in) v out +1v 3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc 6 typical operating characteristics - test circuit v in c in 10uf v out cff v bias c1 0.1uf in bias pok fb out gnd r1 r2 en tj47300 c out 10uf r2 10k circuit #1 circuit #2 circuit #3 circuit #4 circuit #5
3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc 7 ven: 5v/div, vout: 2v/div, 200us/div start up @ iout=10ma, circuit #1 (cff=10nf, r2=10k ? , r1=4.7k ? , v in =3.5v, v bias =5.0v) ven: 5v/div, vout: 2v/div, 200us/div start up @ iout=3.0a, circuit #1 (cff=10nf, r2=10k ? , r1=4.7k ? , v in =3.5v, v bias =5.0v) v en v out v en v out vin: 5v/div, vbias: 5v/div, vout: 2v/div, 500us/div start up with v bias @ iout=10ma, circuit #2 (cff=10nf, r2=10k ? , r1=4.7k ? , v in =3.5v) vin: 5v/div, vbias: 5v/div, vout: 2v/div, vpok: 5v/div, 500us/div start up with v in @ iout=10ma, circuit #2 (cff=10nf, r2=10k ? , r1=4.7k ? , v bias =5.0v) v in v out v bias v in v out v bias ven: 5v/div, vout: 2v/div, 200us/div start up @ iout=10ma, circuit #3 (cff=10nf, r2=10k ? , r1=4.7k ? , v in =3.5v, v bias =5.0v) ven: 5v/div, vout: 2v/div, 200us/div start up @ iout=3.0a, circuit #3 (cff=10nf, r2=10k ? , r1=4.7k ? , v in =3.5v, v bias =5.0v) v en v out v en v out v pok
3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc 8 vbias: 5v/div, ven: 5v/div, out: 2v/div, 2ms/div start up @ iout=10ma, circuit #1 (cff is varied, r2=10k ? , r1=4.7k ? , v in =3.5v, v bias =5.0v) v bias v out v en 10nf 100nf 330nf v bias v out v en vbias: 5v/div, ven: 5v/div, out: 2v/div, 2ms/div start up @ iout=10ma, circuit #5 (cdelay is varied, r2=10k ? , r1=4.7k ? , v in =3.5v) 10nf 100nf vout: 20mv/div, iout: 2a/div, 100us/div load transient response (cff=10nf, r2=10k ? , r1=4.7k ? , v in =3.5v, v bias =5.0v) vout: 20mv/div, iout: 2a/div, 100us/div load transient response (cff=10nf, r2=10k ? , r1=4.7k ? , v in =3.5v, v bias =5.0v) v out i out v out i out vin: 5v/div, vbias: 5v/div, vout: 2v/div, 500us/div start up with v bias @ iout=10ma, circuit #4 (cff=10nf, r2=10k ? , r1=4.7k ? , v in =3.5v) vin: 5v/div, vbias: 5v/div, vout: 2v/div, 500us/div start up with v in @ iout=10ma, circuit #4 (cff=10nf, r2=10k ? , r1=4.7k ? , v bias =5.0v) v in v out v bias v in v out v bias
3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc 9 0.74 0.77 0.80 0.83 0.86 123456 vin [v] vref [v] 0.74 0.77 0.80 0.83 0.86 2.5 3 3.5 4 4.5 5 5.5 6 vbias [v] vref [v] 0 100 200 300 400 500 600 700 0 0.5 1 1.5 2 2.5 3 iout [a] vdrop [mv] vout = 3.0v v out = 3.3v vout = 2.5v v out = 1.5v v ref vs. v in @ v bias =5.5v v ref vs. v bias @ v in =5.5v dropout voltage
3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc 10 application information the tj47300 is a high performance, low dropout linear re gulator, designed for high current application that requires fast transient response. the tj47300 operates from two input supply voltages, significantly reducing dropout voltage. the tj47300 is designed so that a minimum of external component are necessary. bias supply voltage the tj47300 control circuitry is supplied by the bias pin which requires a very low bias current even at the maximum output current level. a bypass capaci tor on the bias pin is recommended to improve the performance of the tj47300 during line and load transi ent. a small ceramic capacitor from bias pin to ground reduces high frequency noise that could be inje cted into the control circuitry from the bias rail. in practical applications, a 1uf capacitor and smalle r valued capacitors such as 0.01uf or 0.001uf in parallel with that larger capacitor may be used to de couple the bias supply. the bias input voltage must be 2.1v above the output voltage, with a minimum bias input voltage of 3.0v. adjustable regulator design an adjustable output device has output voltage ra nge of 0.8v to 3.3v. to obtain a desired output voltage, the following equation can be used two extern al resistors as presented in the typical application circuit. the resistor values are given by; ? ? ? ? ? ? ? ? ? 1 0.8 v r r out 2 1 it is suggested to use r1 values lower than 10k ? to obtain better load transient performances. even, higher values up to 100 k ? are suitable. enable the tj47300 feature an active high enable input (en) that allows on/off control of the regulator. the enable function of tj47300 has hysteresis characteristics. pulling v en lower than 0.4v disables the chip. pulling v en higher than 2.0v enables the output voltage. supply power sequencing in common applications where the power on transient of v in and v bias voltages are not particularly fast (tr > 100us), no power sequencing is required. wher e voltage transient input is very fast(tr<100us), it is recommended to have the v in voltage present before or, at least, at the same time as the v bias voltage in order to avoid over voltage spikes during the power on transient. output capacitors the tj47300 requires an of output capacitance to ma intain stability. the output capacitor must meet both requirements for minimum amount of capacita nce and esr in all ldos application. the tj47300 is designed specifically to work with low esr ceramic output capacitor in space-saving and performance consideration. using a ceramic capacitor which va lue is at least 10uf on the tj47300 output ensures stability. output capacitor of larger capacitance ca n reduce noise and improve load transient response, stability, and psrr. a minimum ceramic capacitor over than 10uf should be very closely placed to the output voltage pin of the tj47300. input capacitor a large bulk capacitance over than 10uf should be closely placed to the input supply pin of the tj47300 to ensure that the input supply voltage does not sag. also a minimum of 10uf ceramic capacitor is recommended to be placed directly next to the in pin. it allows for the device being some distance from any bulk capacitor on the rail. additionally, inpu t droop due to load transients is reduced, improving load transient response. additional capacitance may be added if required by the application.
3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc 11 decoupling (bypass) capacitor in very electrically noisy environments, it is recomm ended that additional ceramic capacitors be placed from vin to gnd. the use of multiple lower value cerami c capacitors in parallel wi th output capacitor also allows to achieve better transient performance and st ability if required by the application. (see fig.1) feed-forward capacitor to get the higher psrr than the inherent performa nce of tj47300, it is recommended that additional ceramic feed-forward capacitor be placed from out pin to fb pin. the capacitance of feed-forward capacitor with range of 10pf to 1uf allows to achieve better psrr performance when required by the application. (see fig.1) fig. 1 application with decoupling & feed-forward capacitor maximum output current capability the tj47300 can deliver a continuous current of 3.0a over the full operating junction temperature range. however, the output current is limited by the restrict ion of power dissipation which differs from packages. a heat sink may be required depending on the maximum power dissipation and maximum ambient temperature of application. with respect to the ap plied package, the maximum output current of 3.0a may be still undeliverable due to the restriction of th e power dissipation of tj47300. under all possible conditions, the junction temperature must be with in the range specified under operating conditions. the temperatures over the device are given by: t c = t a + p d x ca / t j = t c + p d x jc / t j = t a + p d x ja where t j is the junction temperature, t c is the case temperature, t a is the ambient temperature, p d is the total power dissipation of the device, ca is the thermal resistance of case-to-ambient, jc is the thermal resistance of junction-to-case, and ja is the thermal resistance of junction to ambient. the total power dissipation of the device is given by: p d = p in ? p out = {(v in x i in ) + (v bias x i bias )} ? (v out x i out ) the maximum allowable temperature rise (t rmax ) depends on the maximum ambient temperature (t amax ) of the application, and the maximum allowable junction temperature (t jmax ): t rmax = t jmax ? t amax the maximum allowable value for junction-to-ambient thermal resistance, ja , can be calculated using the formula: ja = t rmax / p d = (t jmax ? t amax ) / p d tj47300 is available in sop8-pp package. the therma l resistance depends on amount of copper area or heat sink, and on air flow.
3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc 12 if proper cooling solution such as heat sink, copper plane area, air flow is applied, the maximum allowable power dissipation could be increased. howe ver, if the ambient temperature is increased, the allowable power dissipation would be decreased. the ja could be decreased with respect to the copper plane area. so, the specification of maximum power dissipation for an applicatio n is fixed, the proper copper pl ane area could be estimated by following graphs. wider copper plane area leads lower ja . the maximum allowable power dissip ation is also influenced by the ambient temperature. with the above ja -copper plane area relationship, the maximum a llowable power dissipation could be evaluated with respect to the ambient temperature. as sh own in graph, the higher copper plane area leads ja . and the higher ambient temperature leads lo wer maximum allowable power dissipation. the graph above is valid for the thermal impedance sp ecified in the absolute maximum ratings section on page 1.
3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc 13 the ja could be decreased with respect to the copper plane area. so, the specification of maximum power dissipation for an application is fixed, the proper plane area could be estimated by following graphs. wider copper plane area leads lower ja . the maximum allowable power dissipation is also in fluenced by the ambient temperature. with the ja - copper plane area relationship, the maximum allo wable power dissipation could be evaluated with respect to the ambient temperature. as show n in graph, the higher copper plane area leads ja . and the higher ambient temperature leads lower maximum allowable power dissipation.
3.0a low output voltage ultra ldo re gulator tj47300 2011 preliminary htc 14 preliminary revision notice the information in this datasheet can be revised without any notice.

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